1. Technical Field
The present disclosure relates to a process for making an electric testing of electronic devices.
The present disclosure also relates to a system for making the electric testing of electronic devices.
The present disclosure also relates to a reconfigurable digital interface for making the electric testing of electronic devices.
The disclosure particularly, but not exclusively, relates to a process for making an electric testing of electronic devices, of the type comprising at least one wafer electric selection step chosen among: for example a testing of the electric type on wafer or Electrical Wafer Sort (EWS) or of the Final Test type or even testing of incorporated devices System in Package (SiP), or testing of the Wafer Level Burn-In (WLBI) type too, made under stress and when the temperature varies, or again testing of complex electronic systems, and the following description is made with reference to this field of application by way of illustration only.
2. Description of the Related Art
As it is well known, at present for making an electric testing on wafer or EWS on an electronic device to be tested or Device Under Testing (DUT), a testing apparatus or tester, such as an Automatic Test Equipment (ATE), is electrically connected to the wafer whereon a plurality of electronic components are present to be subjected to the test which are, as it is usually said, selected or tried out by the test. In particular, a probe card is used associated with at least one probe or, more in general, with a plurality of probes, that serves as interface between the ATE and the wafer. The probe card substantially is a board comprising a Printed Circuit Board (PCB) and different tens (often also different hundreds) of probes that electrically connect the ATE to most of the electric terminations or pads, of the device to be tested. In fact, the ATE comprises resources of measure or of testing that are connected to all the pads for making the testing, and the number of pads for making the testing can be smaller or identical to the number of pads of the device. The resources through which the ATE executes measures or tests are made for example of suppliers, signal generators, measure instruments, calculation and processes instruments, etc.
This type of methodology is adopted also for making a Final Test of an electronic device DUT, for which one or more chips are incorporated in a single package, that will be connected for example to a plurality of pogo pins of a socket so that an ATE executes the Final Test thereof.
Similarly, for testing a generic, complex electronic system through the use of an ATE, the resources of this latter are connected to the circuits of the electronic system to be tested through pads, in case chips on wafer are to be tested, or through bumps or leads, in case the chips are also incorporated in a package or in case the chips are on a wafer whereon the bumps are present (for example created on the pads), or, in general, through suitable connectors already present in the circuits being realized according to the prior art.
However, the disadvantages of this type of methodology are multiple. In particular, the testing of complex devices on wafer using this type of methodology is very complicated since more testing operations are executed and thus to contact the wafer more times.
Moreover, the use of probes that connect the ATE to the wafer often implies the damaging of the pads of the selected devices, complicating the successive assembly of the devices themselves.
Moreover, making the testing of more devices connected in parallel requires the use of probe cards with a very high number of probes, increasing the problems of contacting and, thus, of electric continuity between the probes of the probe card and the pads of the DUT and causing also problems of electric performance loss. It is also to be said that the number of resources of the ATE to be used increases according to the number of pads to be contacted on the DUT to be tested and, in consequence, the number of DUT that can be tested in parallel decreases, increasing the costs of the testing.
Within this domain, it is also worth reminding that a generic device to be tested can be made of at least one generic and however complex electronic device or of a group of integrated electronic circuits incorporated in a package, or of a so called System in Package (SiP), or again of a generic electronic system however complex. Moreover, a device DUT can comprise analog and radiofrequency (RF) circuits, digital circuits and one or more different types of memories. By way of example, a generic, complex device DUT comprising a memory block (for example a Flash memory), an analog circuit block, a digital circuit block and an RF circuit block is in general defined with mixed signal since there are both analog and digital signals and also radiofrequency signals.
At present, especially for DUT used in the automotive field, the execution of the testing of devices DUT of such a complex type requires two or more testing operations and, thus, the use of at least two different types of ATE, also under different temperature conditions. In consequence, the process of electric selection is remarkably complicated. In fact, for the testing of complex DUT, ATE of different type and of high cost have to be available and, besides, production problems due to the presence of analog and RF circuits in the DUT have to be solved. For example, for making the testing of a memory block an ATE specific for the memory testing is used, connecting it to a specific portion of the same DUT. It is also possible to make the testing of digital circuits and of memory circuits with a same ATE, connecting a portion of the DUT, in particular the digital and memory blocks, to the corresponding resources of the ATE. Similarly, for making the testing of digital and analog circuits an ATE specific for the testing of mixed signal circuits, i.e., both analog and digital signals, is used connecting a portion of the DUT, in particular the digital and analog blocks, to the corresponding resources of the ATE. Instead, for the testing of the radio-frequency (RF) circuits a specific ATE may be used, connecting another portion of the DUT, in particular the radio-frequency circuits, to the corresponding resources of the same ATE. It is also known that it is possible to make together the testing of the digital, analog and RF circuits by using an ATE specific for the testing of mixed signal circuits that has inside also instruments specific for the testing RF, connecting a part of the DUT, in particular the analog, digital and RF blocks to the resources of the ATE. However, a disadvantage of this type of testing is that the mixed signal ATE have a cost that is in general very high and in any case higher with respect to the other types of ATE, besides being remarkably complex. Moreover, the presence of analog and RF circuits in the DUT makes it difficult the testing due to the various parasite phenomena in the electric measure chain between the DUT and the instruments inside the ATE.
In particular, for making the testing of a digital block an ATE specific for the digital testing is connected to a corresponding digital portion of the resources of the same DUT. For this testing scanning techniques are usually implemented, i.e., the device is provided with scan cells on board of the device for making the boundary scanning (for the input and output pins) and/or internal scan cells (for the internal nodes), connected in series to form scan chains.
In particular, the scan chains are created by modifying, suitably and in a per se known way, the Flip Flops, comprised in a given logic network, for example by arranging at their input a circuit that can be a multiplexer, and thus creating scan Flip Flops being useful during the testing step, or test mode, of the digital circuit. These scan Flip Flops receive at the input a control signal called Scan Mode, or Scan Enable or Scan Selection, useful for making the circuit pass from the test mode configuration to the normal operation configuration, or user mode.
A scan chain consists, thus, in a shift register, that groups together at least part of the memory elements, the flip flops, of the digital circuit. By way of example, the annexed FIG. 1 shows a generic device DUT 101 comprising a digital block 102 comprising at least one scan chain or more in general a plurality of scan chains 103 provided with input terminals, or scan chain inputs or pseudo-primary inputs, and with output terminals, or scan chain outputs or pseudo-primary outputs while the other input and output terminals that are not connected to scan chains will be respectively primary inputs and primary outputs.
For the testing through scan chains suitable software Advanced Test Pattern Generator (ATPG) generate test patterns at the input of the DUT. These patterns, called test vectors or scan vectors or input test vectors, are the values that the memory elements, i.e., the flip flops, of the digital circuit take and they are shifted in serially along the chains for stimulating the internal circuits of the device according also to the value that the primary inputs will take. In response, the values of the primary outputs and the values generated of the output test vectors, or signatures or responses are observed, these values being captured by the scan cells and then shifted out for comparing them with the testing awaited results, or awaited signatures. The single scan vector is thus a sequence of bits having value 0 and 1 that are charged in a scan chain.
As shown in FIG. 2, the test vectors are supplied at the input of the circuit and charged onto the scan chains by the tester ATE 104, that, at the end of the test, discharges the signatures at the output and analyses them. Under steady conditions, while the signatures are shifted out, the new scan vectors are shifted in. Since the number of flip flops arranged in cascade in the scan chains determines the time for charging the vectors and discharging the signatures, it is clear that the less deep the scan chains are, the more reduced the testing time is. Moreover, the testers ATE have a limited number of digital channels or resources to connect the scan chains to, and this number of resources determines the number of scan chains that can be created in the digital block 102 incorporated in the DUT 101. Thus, usually, very expensive and complex resources are available in the ATE for introducing and storing the input test vectors and operating then a comparison with the awaited results.
At present, a frequently used technique being efficient for reducing the depth of the scan chains is the scan compression, that reduces by a factor also higher than 10 the number of scan chains that are connected to the digital tester. In particular, as shown in FIG. 3, this technique provides to connect at the input of the scan chains of the DUT 101 a decompression circuit 105 of the test vectors at the input of the same scan chains and at the output a compression circuit 106 of the signatures at the output of the scan chains.
In consequence, the ATE supplies at the input the compressed test vectors and collects at the output the compressed signatures.
In general the test vectors, generated by the ATPG, are charged by the ATE in the scan chains, for example 10 MHz, while the digital channels of the tester ATE have band often higher than 10 MHz, for example 100 MHz, in accordance with the specifications of the ATE being considered. Thus, to better exploit the characteristics of the ATE, such shift registers and/or multiplexers and/or demultiplexers can be inserted in the digital block of the DUT so as to reduce the number of inputs and of outputs of the digital block to be connected to the ATE. A solution of this type is described, for example, in the US patent application no. 2005/0055617 to Tatung Co LTD.
Hence the frequency of the signals at the input and at the output of the digital signal, and thus at the output and at the input of the ATE, is increased reducing the number of resources of the ATE connected to the single digital circuit. In consequence, the scan chains of the device could operate at a lower frequency, for example 10 MHz, with respect to the frequency of the input signals, for example 80 MHz.
A similar measure allows to increase the execution frequency of the test on the scan chains, as described in U.S. Pat. No. 7,137,053 to Khoche A., Rivoir J., Armstrong D.
To this aim, U.S. Pat. No. 7,428,678 to Cypress Semiconductor Corp., describes a technique for using a single input channel and a single output channel used for the test signals, during the testing step, and for the data signals during the normal operation.
It is also known to modify the connections between the various scan chains according to the used tester, as described in U.S. Pat. No. 6,988,228 to Texas Instruments Inc.
However, a lot of the known solutions reduce the number of channels for making the scanning without reducing the other channels of the DUT that are not used.
Moreover, the digital testing can be made using Low Pin Count (LPC) interfaces useful to reduce the number of pins to be contacted for making the testing and, thus, of signals that an ATE sends to the DUT to be tested.
Moreover, since for making the testing an external clock is used for synchronizing the various parts of the system to be tested, it is suitable to create an interface as much standard as possible and adaptable to the different devices and for different test needs.
Moreover the testing of a specific device is very often linked to the particular type of used ATE and to the specific characteristics of its test resources, and thus it would be suitable to find such a new standard approach as to use for the testing of a same device also ATE of different type or with resources having different characteristics, increasing the flexibility of the productive process with a consequent reduction of the costs.